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This paper presents a system, which generates code for a high speed parallel computer architecture taking as input the tolerance schemes of digital filters. The multi-processor system consists of data-, I/O-processors and a multiport memory. The interconnection network is a crossbar. The data-processors contain a private memory for the program instructions and local register blocks in which intermediate operands are stored. All system components operate synchronously.
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '83. (Volume:8 )
Date of Conference: Apr 1983