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Browse Conference Publications > Acoustics, Speech, and Signal ... Help

Realization of digital filter algorithms by use of a high speed parallel processing architecture

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4 Author(s)
Steinmetz, R. ; Institut fuer Uebertragungstechnik, Darmstadt, Merckstr, FRG ; Gemballa, R. ; Lenzer, J. ; Roth, H.

This paper presents a system, which generates code for a high speed parallel computer architecture taking as input the tolerance schemes of digital filters. The multi-processor system consists of data-, I/O-processors and a multiport memory. The interconnection network is a crossbar. The data-processors contain a private memory for the program instructions and local register blocks in which intermediate operands are stored. All system components operate synchronously.

Published in:
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '83.  (Volume:8 )

Date of Conference: Apr 1983

Page(s):
1188 - 1191
Digital Object Identifier :
10.1109/ICASSP.1983.1171973
Product Type:
Conference Publications

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