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Design of a multistage switching network for ATM

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2 Author(s)
H. S. Kim ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada ; A. Leon-Garcia

The authors propose a switching network that approaches a maximum throughput of 100% as buffering is increased. This self-routing switching network consists of simple 2×2 switching elements, distributors, and buffers located between stages and in the output ports. The switching network requires a speedup factor of two. The switch has log2 N stages that move packets in store-and-forward fashion, thus incurring a latency of log2 N time periods. The performance analysis of the switch under a uniform traffic pattern shows that the additional delay is small and a maximum throughput of 100% is achieved as buffering is increased

Published in:

Communications, 1990. ICC '90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on

Date of Conference:

16-19 Apr 1990