Phase and delay extraction in Q/sup 2/PSK: ML receivers using systolic array processing

A maximum likelihood decision-directed (MLDD) receiver structure is derived for a data-transmission system which employs quadrature-quadrature phase-shift keying (QQPSK) as the modulation scheme. The receiver is derived by treating the problems of sequence decision, sample timing, and carrier phase as a composite estimation problem. It is shown that the resulting maximum likelihood estimates are asymptotically unbiased. Cramer-Rao lower bounds are derived for the estimates and plotted for different cases. Symbol detection is carried out by means of a modified Viterbi algorithm, and a parallel structure is developed for estimating carrier phase and delay time for high-speed data transmission. It is shown that the resulting synchronizer can be simplified for application in data systems using QAM (quadrature amplitude modulation). Interaction between detection and synchronization is studied. It is shown that the parallel estimator is well-suited for high-speed digital signal processing and lends itself easily to systolic array implementation.<
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