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A general purpose real time digital speech processor

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4 Author(s)
Mohiuddin, K. ; Stanford University, Stanford, CA ; Narayan, S. ; Chen, K. ; Peterson, A.

The architecture of a real time processing system to study and compare a number of different speech processing algorithms is described. The system consists of a front-end processor, a fast arithmetic processor and a diagnostic/download processor. The arithmetic processor is based on bit-slice bipolar microprocessor devices. It has a dual bus structure with a dual ported data memory and employs horizontal type microprogramming with a writable control store. A variable rate clock is used to avoid pipeline delays in data paths; the effective computation rate is about 5 million instructions per second. Input-output operations are done by the front-end processor in conjunction with a double buffered I/O memory. The user program is loaded into the control store from a host system using the download processor which also provides extensive debugging capabilities. Three different algorithms-a Linear predictive coder (LPC), an Adaptive Transform Coder, (ATC) and a wave form coder--have been implemented on the system. The performance of the processor with respect to these algorithms will be discussed.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '81.  (Volume:6 )

Date of Conference:

Apr 1981