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Design of a multistage decimation-interpolation filter

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1 Author(s)
V. Hansen ; Tektronix, Inc., Beaverton, OR

A 2 chip digital multi-rate FIR filter implemented in 2 micron CMOS performs 10 million multiplications and 20 million accumulations per second. The filter has 48 programmable bandwidths in a 1-2-5 sequence, and can either interpolate or decimate. This paper describes the design and implementation of the filter.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.  (Volume:12 )

Date of Conference:

Apr 1987