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The investigation of parallel computer architectures and parallel algorithms for speech recognition is important. Large vocabulary speech recognition is a computationally intensive problem, which can require orders of magnitude acceleration over a single processor to achieve real-time performance. Also, there is still much algorithm development work to be done, which requires a programmable computer rather than a fixed hardware implementation. This paper describes progress on the ASPEN parallel computer, that is applicable to signal understanding problems in general and large-vocabulary speech recognition in particular. The following will be described in this paper: the hardware architecture; the software architecture; classes of pattern recognition algorithms that are well-suited to the architecture; examples from speech recognition.