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A simplified low-voltage smart power technology

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6 Author(s)
Berta, F. ; Centro Nacional de Microelectronica, Barcelona, Spain ; Fernandez, J. ; Hidalgo, S. ; Godignon, P.
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A novel self-isolated low-voltage smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to the gate.<>

Published in:

Electron Device Letters, IEEE  (Volume:12 ,  Issue: 9 )