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On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011

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9 Author(s)
van Wijk, F. ; Philips Research Laboratories, Eindhoven, The Netherlands ; Welten, Frank P. ; van Meerbergen, J. ; Stoter, J.
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A 2µm CMOS Digital Signal Processor (PCB5010 / PCB5011), capable of eight million instructions per second (8MIPS), and up to 6 concurrent operations in each instruction will be described [1]. This high throughput results from a highly parallel architecture (see Fig. 1) with high-speed data handling capability. It contains two 16b data buses, two primary execution units, five I/O interfaces, a data ROM, two data RAMs, and flexible addressing of on and off-chip memory using three address computation units. Benchmarks show a two to six times improvement in overall performance over its predecessors.

Published in:

Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '86.  (Volume:11 )

Date of Conference:

Apr 1986

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