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The fortunes of signal processors are directly related to progress in integrated circuit technology. This technology has experienced recent advances in logic design density and increased clock rates that will have significant impact on the performance of signal processors for the next 4 to 5 years. The objective of this paper is to develop an architecture that is matched to the computational requirements of a typical RADAR system and show how it can be implemented with these new devices. An analysis has been conducted to determine the relationship between multiplications, additions, and memory accesses for those algorithms requiring the highest data throughput including an adaptive array process. An architecture for a signal processing engine is then developed that is matched to the relative ratios for these functions. This signal processing engine is then sized using configurable gate array integrated circuits to implement each of it's major functions. Finally, an estimate is made of the number of engines required to process these algorithms.