By Topic

Analysis and optimization of substrate noise coupling in single-chip RF transceiver design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Koukab, A. ; Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland ; Banerjee, K. ; Declercq, M.

The relentless move toward single chip integration of RF, analog and digital blocks results in significant noise coupling effects that can degrade performance and hence, should be controlled. In this paper, we propose a practical methodology that uses a suite of commercial tools in combination with a high-speed extractor based on an innovative semi-analytical method to deal with noise coupling problems, and enable RF designers to achieve first silicon-success for their chips. The integration of the methodology in a typical RF design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002