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Optimization and control of VDD and VTH for low-power, high-speed CMOS design

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1 Author(s)
T. Kuroda ; Dept. of Electr. Eng., Keio Univ., Yokohama, Japan

It is essential to control supply voltage VDD and threshold voltage VTH for low power, high-speed CMOS design. In this paper, it is shown that these two parameters can be controlled by designers as objectives of design optimization to find better trade-offs between power and speed. Quantitative analysis of trade-offs between power and speed is presented. Some of the popular circuit techniques and design examples to control VDD and VTH are introduced. A simple theory to compute optimum multiple VDD and VTH values is described. Scaling scenarios of variable and/or multiple VDD and VTH values is discussed to show future technology directions.

Published in:

Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on

Date of Conference:

10-14 Nov. 2002