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Program control flow transfer (branch) prediction is considered to be a performance hurdle and a key design issue for current and future microprocessors. Branch prediction schemes with high prediction accuracy have been proposed to support longer processor pipelines with higher frequency clocks. In the previously published literature, the design and evaluation of branch predictors have been based heavily on the simulation of only user instructions from scientific and commercial workloads written in programming languages such as C or C++. To complement the existing research, the paper presents a case study of the modeling and evaluation of advanced branch predictors using full-system simulation of Java workloads running on a commercial operating system. The contributions of the paper are: (1) the presentation of a full system simulation framework to model, simulate and evaluate the performance of a set of advanced prediction schemes on emerging Java workloads; (2) an analysis of the performance and design complexity of advanced branch predictors in the presence of full system code; (3) an accurate modeling of user/kernel branch aliasing on a wide range of branch predictors.