New approaches for simulation of wafer fabrication: the use of control variates and calibration metrics

Simulation-based wafer fabrication optimization models require extensive computational time to obtain accurate estimates of output parameters. This research seeks to develop goal-driven optimization methodologies for a variety of semiconductor manufacturing problems using appropriate combinations of "resource-driven" (R-D), "job-driven" (J-D), and mixed (combination of R-D and J-D) models to reduce simulation run times. The initial phase of this research investigates two issues: (a) the use of the R-D simulation control variates for the J-D simulation and (b) development of metrics that calibrate the output from the R-D and J-D modeling paradigms. The use of the R-D model as a control variate is proposed to reduce the variance of J-D model output. Second, in order to use the R-D model output to predict the J-D model output, calibration metrics for the R-D and J-D modeling approaches were developed. Initial developments were tested using an M/M/1 queuing system and an M/D/1 queuing system.