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We present a fast algorithm and its single chip VLSI implementation for generating moments of two-dimensional (2-D) digital images for real-time image processing applications. Using this algorithm, the number of multiplications for computing 16 moments of a 512 × 512 image is reduced by more than 5 orders of magnitude compared to the direct implementation; the number of additions is reduced by a factor of 4. This also makes the software implementation extremely fast. Using the chip, 16 moments μp,q(p = 0, 1, 2, 3, q = 0, 1, 2, 3) of a 512 × 512 8 bits/pixel image can be calculated in real time (i.e., 30 frames per second). Each moment value is computed as a 64- bit integer. The basic building block of the algorithm is a single-pole digital filter implemented with a simple accumulator. These filters are cascaded together in both horizontal and vertical directions in a highly regular structure which makes it very suitable for VLSI implementation. The chip has been implemented in 2.5 μ CMOS technology, it occupies 6100 μm × 6100 μm of silicon area. The chip can also be used as a general cell in a systolic architecture for implementing 2-D transforms having polynomial basis functions.
Acoustics, Speech and Signal Processing, IEEE Transactions on (Volume:34 , Issue: 3 )
Date of Publication: Jun 1986