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A class of completely-pipelined VLSI architectures is defined. Two topologies are then described: leaf-connected trees and mesh-connected trees. The leaf-connected tree structure is used to construct a completely-pipelined bit-serial multiplier and a completely-pipelined word-serial, bit-serial convolver. The mesh-connected tree structure is used to implement completely-pipelined bit-parallel multiplication and completely-pipelined word-parallel bit-parallel convolution. Layouts are described that are within log factors of asymptotic optimality. It is shown that, asymptotically, the area required for power distribution actually dominates the rest of the area for a wide class of structures. This illustrates the importance of studying the constants of proportionality in evaluating area, time, and energy requirements, and suggests that the choice of topologies may very well depend on the fabrication technology. The importance of parameterized and high-level design is stressed throughout. Also stressed is the idea of applying sound architectural technique at all levels of information organization, including, in particular, the bit level.