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Fourth-order bandpass recursive digital filters, realized in cascade form, are implemented in a 16-bit microprocessor, enabling sampling frequencies up to 3.3 kHz, with the use of the processor's multiply instruction. The design did not follow the usual choice of canonical forms and scaling within the filter structure. On the contrary, the input wordlength is set at 12 bits and the filters are allowed to have gains up to 16. This design method provided the required output signal-to-noise ratio and shorter computation time when compared to the scaling design, since the filters can be realized with only 4 multiplications per cycle. It was found that the filter's internal magnification is a function of the transformation used to arrive at the filter Z plane transfer function. The design parameters for the filters used in the analysis of sleep electroencephalograms (EEG's) are also presented.