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An algorithm is presented that introduces two degrees of parallelism into the implementation of fast Fourier transform (FFT) processors. That is, both the radix of factorization and the number of arithmetic units may be selected to achieve the required processing speed. A serial vector multiplier that is ideally suited to the implementation of a general radix arithmetic unit is described. It is subsequently shown that a fast Fourier processor having an attractive cost performance ratio can be built by employing serial arithmetic in the implementation of the algorithm developed.