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The subject of this paper concerns the analysis of high-radix FFT algorithms appropriate to hardware implementation of nonrecursive filters and the error propagation properties associated with these algorithms. Variations in the structure of high-radix fast Fourier transforms are illustrated by means of their Kronecker product expansions. The implications in hardware design of the different structures are discussed. These implications include tradeoffs between memory size and throughput rate as shown by Comparison of the logic organizations of serial and cascade fast Fourier processors. It is shown that in a high-radix cascade processor, significant reduction in memory can often be obtained with a modest increase in complexity of the arithmetic units. The relationship between the permutation matrices specified in a Kronecker factorization, and the structure and addressing of memory is brought out. As an example, the implementation of a nonrecursive digital filter is included using a radix-4 factorization which provides for an extremely simple memory organization. The permutation matrix is such that both data storage and addressing are provided using serial MOS shift registers. In order to compare the accuracy of high-radix algorithms relative to the base-2 algorithm, a fixed-point simulation study of the error propagation properties was conducted of a full radix-4 and a radix-16 FFT for N= 1024 and 256, respectively. The computational errors were compared with corresponding results obtained from the base-2 algorithm. The results of the simulations were also compared with a model which is a modification of that reported by P. D. Welch. The modification consists of the representation of roundoff error buildup in the radix-2 and radix-4 FFT in closed form by a nonhomogeneous difference equation. The illustrative example chosen is the lower bound discussed by Welch.