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A high-level data path allocation algorithm based on BIST testability metrics

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2 Author(s)
Tianruo Yang, L. ; Dept. of Comput. Sci., St. Francis Xavier Univ., Antigonish, NS, Canada ; Muzio, J.

In this paper, we describe a BIST testability metric-based high-level data path allocation algorithm to facilitate Built-In Self-Test designs. We will describe register transfer level data path testability metrics to evaluate various BIST configurations and make improvement decision during the data path allocation. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.

Published in:

Microelectronics, The 14th International Conference on 2002 - ICM

Date of Conference:

11-13 Dec. 2002