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An integrated system is presented combining a rule-based symbolic code simplification system and a fine-grain code scheduler for a multiprocessor based on a ring/mesh of commercial single-chip digital signal processing (DSP) processors. The code simplification component uses a priori information to direct the application of symbolic simplification rules to local or global code segments of the original program. The code generation includes graph parsing, optional blocking, and code scheduling with partial backtracking. Resource allocation is incorporated with operation scheduling to increase the total performance of the practical system. The integrated system can implement many DSP algorithms, generating very efficient code for a variety of DSP processor configurations
Published in:
Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on
Date of Conference: 3-6 Apr 1990
- Page(s):
- 1053 - 1056 vol.2
- Meeting Date :
- 03 Apr 1990-06 Apr 1990
- ISSN :
- 1520-6149
- INSPEC Accession Number:
- 3864248
- Conference Location :
- Albuquerque, NM
- Digital Object Identifier :
- 10.1109/ICASSP.1990.116093
- Product Type:
- Conference Publications
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