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A ΔΣ fractional-N frequency synthesizer for the 2-GHz-range wireless communication applications is implemented in a 0.35-μm BiCMOS process, using only CMOS components. The synthesizer achieves a close-in phase noise of -81 dBc/Hz, while the spurious tones are at -85 dBc. The synthesizer features a multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation. The entire prescaler, including the gigahertz-speed first stages, is implemented using full-swing logic. The current source structure employed in the charge pump provides a constant output current over a wide, almost rail-to-rail output voltage range. The power dissipation of the synthesizer chip is 22.6 mW from a 2.7-V supply.