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Electrostatic discharge (ESD) accounts for over 30% of chip failure which occurred during chip manufacturing. Inadvertent touching by human body or contact with assembler tray can lead to such ESD failures. The most dominant ESD model is the charged-device model (CDM) wherein energy-destructive failure is incorporated resulting from rapid inflow, or outflow, of high current. Conventional modeling and simulations of the CDM are engineered to describe the behavior of ESD protection circuits, hence have a limitation to account for chip-level charge transfer. This paper presents a new methodology to simulate CDM behavior at chip level. A hierarchical approach associated with a CDM macromodel is developed to model a full-chip structure comprised of several functional subsystems and multiple power supplies. Full-chip CDM simulation provides the analysis of chip-level discharge paths and failure mechanisms, especially focusing on the gate oxide reliability. The proposed method can easily be applied to the CDM failure analysis of any product ICs in the early design stage. As an example, simulation results of a mixed-signal application-specific integrated circuit processed in a 0.25-μm CMOS technology show high correlation with the measurement data.