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Time delay, crosstalk and repeater insertion models for high performance SoC's

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3 Author(s)
R. Venkatesan ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; J. A. Davis ; J. D. Meindl

Using a new physical model for the transient response of a distributed RLC interconnect with a capacitive load, novel compact expressions have been derived for: (1) the time delay, (2) the peak crosstalk for coupled lines, (3) the optimum number and size of repeaters, and (4) the time delay for repeater-inserted distributed RC and RLC lines. For practical ranges of line parameters, the maximum error between the compact models for time delay and crosstalk, and HSPICE simulations are 2% and 10% respectively. These new models are used to define a design space that illustrates a novel trade-off between number of repeaters and wire cross-section to achieve specified delay and crosstalk targets. For a 3 cm long interconnect, inserting 8 repeaters decreases peak crosstalk by 51% and wire cross sectional area by 83% without increasing the time delay, compared to a design without repeaters.

Published in:

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Date of Conference:

25-28 Sept. 2002