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Analytical performance models for RLC interconnects and application to clock optimization

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5 Author(s)
Xuejue Huang ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Yu Cao ; Sylvester, D. ; Tsu-Jae King
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A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

Published in:

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Date of Conference:

25-28 Sept. 2002