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Impact of technology scaling and packaging on dynamic voltage scaling techniques

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4 Author(s)
Duarte, D. ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; Vijaykrishnan, N. ; Irwin, M.J. ; Tsai, Y.-F.

This paper studies how the effectiveness of various dynamic voltage scaling mechanisms is affected by technology scaling and system activity. We show that Vdd scaling maintains its effectiveness while Vth scaling and supply gating become more efficient as the feature size decreases. We also discuss the impact of packaging and. provide tools for bringing it early into the design process. In this way, short-term and long-term savings are identified, with the latter providing additional energy savings up to 10.2%, on average.

Published in:

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Date of Conference:

25-28 Sept. 2002