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Highly efficient digital CMOS accelerator for image and graphics processing

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2 Author(s)
Margala, M. ; Electr. & Comput. Eng. Dept., Rochester Univ., NY, USA ; Rong Lin

This paper presents a novel high-bandwidth digital accelerator for image and graphics processing applications. The proposed architecture outperforms previously proposed processing-in-memory architectures in speed, area and power by up to several orders of magnitude. Several variations of the design have been implemented in 2.5 V 0.25 μm and 1.8 V 0.18 μm CMOS technology.

Published in:

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Date of Conference:

25-28 Sept. 2002