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An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

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4 Author(s)
Seung-Chan Heo ; Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea ; Young-Chan Jang ; Sang-Hune Park ; Hong-June Park

An 8-bit 200 MSample/s CMOS folding/interpolating ADC chip was implemented by using a 0.35-μm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published folding/interpolating ADC chips. The delay time of digital encoder block was reduced to 1.3 ns from 2.2 ns by using a DCVSPG-style differential logic. The chip area and the measured power consumption were 1.02 mm2 and 120 mW respectively at the supply voltage of 3.3 V.

Published in:

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Date of Conference:

25-28 Sept. 2002