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An ECL gate array hardened against soft errors

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5 Author(s)
Okabe, M. ; Mitsubishi LSI Research and Development Laboratory, Hyogo, Japan ; Tatsuki, M. ; Sakaue, K. ; Hirao, T.
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A 1.3μm gate array whose soft error rate is improved by a factor of 100 over a conventional design will be reported.

Published in:
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International  (Volume:XXX )

Date of Conference: 0-0 Feb. 1987

Page(s):
152 - 153
Conference Location :
New York, NY, USA
Digital Object Identifier :
10.1109/ISSCC.1987.1157091
Product Type:
Conference Publications

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