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A 3.6ns ECL programmable array logic IC

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2 Author(s)
M. Millhollan ; National Semiconductor Corp., Santa Clara, CA, USA ; Chiakang Sung

An ECL FPAL with a total delay of 3.6ns at 1.0W will be reported. The chip has 64 product terms with 16 inputs and 8 outputs.

Published in:

Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International  (Volume:XXVIII )

Date of Conference:

13-15 Feb. 1985