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A 64Kbit CCD memory

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2 Author(s)
Varshney, R. ; Fairchild Camera and Instrument Corp., Palo Alto, CA, USA ; Venkateswaran, K.

This paper will cover the design and performance of a 64Kbit buried channel CCD memory, operating over 1-5MHz, and using 8-phase ripple clocks within an interlaced series-parallel-series structure. Chip size is 4.4 × 5.8mm2, packaged in a standard 16-pin 300-mil wide assembly.

Published in:

Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International  (Volume:XXI )

Date of Conference:

15-17 Feb. 1978