Referenced Items are not available for this document.
A graph-theoretical method, with wiring and placement problems considered simultaneously, will be discussed. The approach has resulted in the development of a computer program affording automatic layout design of single-layer IC chips on smallest possible areas.
Published in:
Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International
(Volume:XIII
)
Date of Conference: 18-20 Feb. 1970
- Page(s):
- 86 - 87
- Conference Location :
- Philadelphia, PA, USA
- Digital Object Identifier :
- 10.1109/ISSCC.1970.1154803
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
