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A new min-cut placement algorithm for timing assurance layout design meeting net length constraint

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3 Author(s)
Terai, M. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Takahashi, K. ; Sato, K.

A new VLSI min-cut placement algorithm is presented for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays, called GALOP. The application results are described for the case of clock skew control of an ECL 12K-gate array

Published in:

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Date of Conference:

24-28 Jun 1990

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