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An appropriate sampling of devices and architectures for onboard TDMA (Time Division Multiple Access) equipment, burst modems, baseband switches, and SCPC (Single Channel per Carrier) multicarrier demodulators from the present to the year 2000 are selected and presented along with device technology development trends, in terms of minimizing onboard weight and power consumption. The results show that at the present time (equivalent to around the year 1990 for onboard use), onboard TDMA equipment with a clock rate of lower than 100 MHz can be reasonably realized by parallel-processed CMOS/BULK LSIC's, while for TDMA equipment with clock rates of higher than 100 MHz, bipolar devices are more appropriate. The boundary clock rate is not so rigid, and toward the year 2000, the boundary will move up to about 200 MHz. Moreover, around the year 2000, GaAs devices will be more widely used for onboard high-bit rate TDMA. It is shown that for carrier frequencies up to 2 GHz, modem implementation in monolithic microwave IC's is most suitable. Moreover, it is found that coherent demodulation will not entail a big penalty in hardware size and power consumption, because of implementing carrier recovery circuits using IC's and LSIC's. As potential baseband switch configurations, a single -stage and architecture are compared, and suitable throughputs and TDMA frame lengths for each architecture are clarified. For SCPC multicarrier demodulators, the selection of demodulation schemes depends on the number of channels available for regeneration onboard the satellite. Therefore, in this paper, for years 1990, 1995, and 2000, the total weight and power consumption for several suitable onboard multicarrier demodulation schemes are studied as a function of the number of channels to be regenerated.