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A Discrete Fourier-Cosine Transform Chip

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2 Author(s)
Vetterli, M. ; Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland ; Ligtenberg, A.

An 8-point Fourier-cosine transform chip designed for a data rate of 100 Mbits/s is described. The top-down design is presented step by step, including algorithm modification for VLSI suitability, architectural choices, testing overhead, internal precision assignments, mask generation, and finally, verification of the layout. A high-level language (C) design tool was developed concurrently with the layout. This tool allows mimicking exactly the different representations of the algorithm: software, mask, and chip. This provides an automatic cross-checking at all design stages. The VLSI environment created by this tool, as well as existing powerful CAD tools, made a fast design-time possible.

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Selected Areas in Communications, IEEE Journal on  (Volume:4 ,  Issue: 1 )