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Fast Error Decoding with Binary VLSI Logic

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1 Author(s)
D. Mandelbaum ; P. O. Box 645, Eatontown, NJ

Maximal distance binary codes that are composed of individual characters from the residues of pairwise prime polynomials are constructed and compared to Reed-Solomon codes. Although these binary residue codes are not as efficient as R-S codes in that codeword lengths are shorter, error decoding involves only binary and not finite field operations and thus allows faster decoding and greater data rates. Data rates of hundreds of megabits per second are feasible if decoding is implemented with VLSI array logic. Constructions of array logic for use in decoding are described. These codes lend themselves for use in a concatenated coding scheme.

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IEEE Journal on Selected Areas in Communications  (Volume:4 ,  Issue: 1 )