By Topic

On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Gambe, H. ; Tech. Development Dept.,Fujitsu Labs. Ltd., Kawasaki, Japan ; Ikezawa, T. ; Matsumura, T. ; Tsuda, T.
more authors

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.

Published in:

Selected Areas in Communications, IEEE Journal on  (Volume:3 ,  Issue: 2 )