Referenced Items are not available for this document.
This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.
Published in:
Selected Areas in Communications, IEEE Journal on
(Volume:3
,
Issue:
2
)
Date of Publication: Mar 1985
- Page(s):
- 357 - 368
- ISSN :
- 0733-8716
- Digital Object Identifier :
- 10.1109/JSAC.1985.1146206
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Mar 1985
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