By Topic

TDRC-a symbolic simulation based design for testability rules checker

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Varma, P. ; Teradyne, Santa Clara, CA, USA

A symbolic simulation methodology that can be used to verify a set of standard scan-path-based, ad hoc, and boundary-scan design-for-testability (DFT) rules is proposed, and a DFT rule checker, TDRC (testability design rule checker), that uses this methodology is described. In this methodology, symbolic tokens are used to represent the types of signals applied to the primary inputs of the circuit, and, in a process analogous to simulation, these tokens are propagated through the circuit using a set of simulation rules. A check is then made to verify that the required tokens have been propagated to each scan element and that only allowed tokens have reached particular element and circuit ports. The proposed simulation methodology differs from previous path-tracing approaches in that symbolic tokens are propagated to the output of an object, possibly in modified form, depending on the other tokens reaching both the inputs and the logical function of the object. TDRC has been successfully used to identify real problems in real ASIC (application-specific integrated-circuit designs)

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990