On the evaluation of process-fault tolerance ability of CMOS integrated circuits

Some algorithms and applications of inductive fault analysis (IFA) for the design of process-induced fault-tolerant VLSI CMOS circuits are presented. Starting from a mask-level IC design, the IFA procedure extracts all circuit-level faults which may result in the induction of a parasitic physical defect owing to an impure process fabrication. Algorithms concerning the fault list extraction, the density-fault map, and layout-to-schematic tools are detailed and illustrated through comprehensive examples. Applications of IFA cover validation of fault models, better fault coverage of test pattern sets, optimization of process fault-tolerant designs, and evaluation of the effectiveness of new design strategies.<
>