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A novel built-in self-repair approach to VLSI memory yield enhancement

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2 Author(s)
P. Mazumder ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; J. S. Yih

The feasibility of implementing electronic neural networks as intelligent hardware for memory array repair is demonstrated. In particular, it is shown that the neural network control possesses a robust and degradable computing capability under various fault conditions. A yield analysis performed on 64K DRAMs shows that the yield can be improved from as low as 20% to near 99% owing to the self-repair design, with an overhead of no more than 7%. Simulation shows that the neural net algorithms are superior to the Repair Most algorithm

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990