By Topic

Direct access test scheme-design of block and core cells for embedded ASICs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Immaneni, V. ; Intel Corp., Chandler, AZ, USA ; Raman, S.

Intel requires the use of a direct-access test scheme in embedded-core or block-based ASIC (application-specific integrated-circuit) designs. This scheme provides for separate testing of individual block or core cells using proven test vectors. The authors discuss the design modifications for block cells with low pin counts, user application blocks, and large cores with high pin counts. The implementation and verification of the direct-access test scheme in a block- or core-based embedded ASIC design are also briefly described

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990