By Topic

Testing for parametric faults in static CMOS circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ferguson, F.J. ; Dept. of Eng., California Univ., Santa Cruz, CA, USA ; Taylor, M. ; Larrabee, T.

The authors compare the cost of testing for excess of I DDQ caused by bridge, break, and transistor stuck-on faults versus the cost of traditional testing methods. It is shown that, since many defects, cause nonlogical faults, IDDQ monitoring during the application of test vectors to an IC provides significantly higher defect coverage than using only conventional testing. The costs for IDDQ testing are compared with those for SSF (single-stuck-at-fault) testing by modifying an existing SSF ATPG (automatic test pattern generation) system. It is concluded that test generation for IDDQ faults is quicker and more complete than for equivalent SSF faults, and even without explicit IDDQ test generation, I DDQ monitoring can be added to existing SSF testing for increased defect coverage

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990