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Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets

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4 Author(s)
R. R. Fritzemeier ; Sandia Nat. Lab., Albuquerque, NM, USA ; J. M. Soden ; R. K. Treece ; C. F. Hawkins

The authors discuss the significant improvements that were achieved when a conventional ATPG (automatic test pattern generation) algorithm was modified to generate test sets suitable for IDDQ testing. These improvements include increased SAF (stuck-at-fault) coverage, reduced vector set sizes, coverage of logically redundant SAFs and multiple SAFs, increased coverage of CMOS IC non-SAF defects, and reduced CPU cost for ATPG and fault simulation. This reduction in computational complexity for IDDQ based ATPG enables test generation for much larger circuits than previously possible. Additionally untestable faults can be further categorized to identify SAFs that are truly `don't-care faults,' thereby offering a more realistic assessment of actual fault coverage

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990