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Arrangement of latches in scan-path design to improve delay fault coverage

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2 Author(s)
Mao, W. ; Dept. of Electr. & Comput. Eng., Colorado Univ., CO, USA ; Ciletti, M.D.

A problem involving the arrangement of latches in a scan-path design to improve the coverage of delay faults is described. The problem is NP-hard, and a heuristic algorithm is introduced for solving this arrangement problem. A necessary and sufficient condition is also given to determine whether there is a scan path to implement a given delay-fault test pair. Only LAM (latch-arrangement-mapping) implementable test pairs need to be simulated by a delay-fault simulator for a semi-completed LSSD (level-sensitive-scan-design) circuit. Preliminary experimental results show that the proposed algorithm can find a LAM with better fault coverage than a randomly selected ones

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990