Cart (Loading....) | Create Account
Close category search window
 

Design of scan-testable CMOS sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Bong-Hee Park ; Dept. of Electr. & Comput. Eng., Massachusett Univ., Amherst, MA, USA ; Menon, P.R.

It is shown that the detectability of stuck-open faults in CMOS sequential circuits with scan paths containing ordinary shift register latches depends on the state assignment used. A method by which any state table can be realized by a circuit that is scan testable for stuck-open faults is presented. Tests can be applied to these circuits by shifting in only one vector per test, reducing the test application time. The proposed method is applied to five state tables from the MCNC Logic Synthesis and Optimization Benchmarks. It is found that the overhead of the method is in the range of 14% to 29%

Published in:

Test Conference, 1990. Proceedings., International

Date of Conference:

10-14 Sep 1990

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.