Close category search window
 

Zero defects or zero stuck-at faults-CMOS IC process improvement with IDDQ

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Soden, J.M. ; Sandia Nat. Lab., Albuquerque, NM, USA ; Fritzemeier, R.R. ; Hawkins, C.F.

The authors suggest that continuous quality improvement with the goal of zero defects requires a physical defect metric which goes beyond 100% SAF (stuck-at-fault) coverage. It is further suggested that I DDQ testing is a highly efficient technique for detecting most dominant types of CMOS IC defects and therefore should be considered for the manufacture of high-quality, high reliability CMOS ICs

Published in:
Test Conference, 1990. Proceedings., International

Date of Conference: 10-14 Sep 1990

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.