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Implementation of analog neural networks

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2 Author(s)
Hasler, P. ; Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ, USA ; Akers, L.A.

The topics discussed are: architectures of analog neural networks; multilevel or analog DRAM synapses; and a continuous time neural network using a high performance multilevel DRAM system. Neural networks must be implemented in hardware to achieve real time performance. The size and performance of the synapse element play a critical role in the overall system performance. In addition, a long term analog memory circuit is critical for most analog neural network implementations. Dynamic refreshing schemes potentially allow very compact synapses with fast read and write operations, but are only achievable with state of the art analog VLSI design theories and techniques. The implementation described performs an 8 to 10 bit transmission of a dynamically stored value and a 2 MHz, successive approximation analog-to-digital (A/D)→digital-to-analog (D/A) converter

Published in:

Computers and Communications, 1991. Conference Proceedings., Tenth Annual International Phoenix Conference on

Date of Conference:

27-30 Mar 1991