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A low-cost FPGA implementation of the Advanced Encryption Standard algorithm

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2 Author(s)
Zigiotto, A.C. ; Divisao de Engenharia Eletronica, Inst. Tecnologico de Aeronaut., Sao Jose de Campos, Brazil ; d'Amore, R.

This work presents an architecture for a hardware implementation of the Rijndael block cipher with 128-bit key. Rijndael block cipher was recently adopted by the United States government as the new Advanced Encryption Standard (AES). The proposed architecture was designed for low-cost, mid-density FPGA.

Published in:

Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on

Date of Conference:

2002