Referenced Items are not available for this document.
This paper proposes a new method for reducing the test length for digital circuits by adopting an architecture derived from the popular scan approach. An evolutionary optimization algorithm is exploited to find the optimal solution. The proposed approach was tested on the ISCAS89 standard benchmarks and the experimental results show its effectiveness.
Published in:
Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Date of Conference: 2002
- Page(s):
- 89 - 94
- Print ISBN:
- 0-7695-1807-9
- INSPEC Accession Number:
- 7516547
- Digital Object Identifier :
- 10.1109/SBCCI.2002.1137642
- Product Type:
- Conference Publications
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