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VLSI Packaging Technique Using Liquid-Cooled Channels

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2 Author(s)
Kishimoto, T. ; Electrical Communications Laboratories ; Ohsaki, T.

A new packaging technique which employs innovative indirect liquid cooling is described. The technique involves mounting very large-scale integrated (VLSI) chips on a multilayered alumina substrate which incorporates very fine coolant channels. In particular, an investigation into the optimal structure for the cooling section by computer simulation and by experiment involving the physical implementation of this structure is discussed. The numerical solution of the coolant flow distribution obtained ensures that the coolant distributor and collector structure dimensions can be determined to meet the uniform velocity distribution condition. Additionally, the channel cross section is designed to be 800 um wide x 400 um high to achieve a lower thermal resistance. An outline of an indirect liquid cooling package fabricated based on the results of these structures is presented. The package mounts a 5 x 5 array of 8-mm2VLSI chips on a substrate measuring 85 mm x 105 mm. The substrate features 29 very fine coolant channels, six conductor layers, and 900 input/output (I/O) pins. The technique permits the realization of an allowable heat dissipation higher than 400 W per package at a flow rate of 1.0 1/min. Furthermore, since the thickness of the cooling section is smaller than 1.0 mm, the volume power density increases 17 kW/l or more. This cooling capability is tenfold greater than that obtained by conventional indirect water cooling.

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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on  (Volume:9 ,  Issue: 4 )