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Plastic encapsulation of large semiconductor chips has resulted in increased stress-related failures such as cracked passivation, metal deformation and delamination, cracked chips, cracked packages, and parameter shifts. The large mismatch in the coefficient of thermal expansion between the silicon chip and the plastic encapsulant is felt to be the major contributor to these failures. In an effort to minimize stress problems, many mold compound manufacturers have modified their formulations and epoxy resin chemistries. As a result, many "low-stress" mold compounds have been introduced in recent years. A procedure was developed for screening encapsulation plastics for mechanical stress on semiconductor chips. The method involves temperature cycling of molded packages containing unpassivated test chips. The degree of deformation of the metallization is used as a measure of stress on the chip. Several semiconductor grade epoxy mold compounds were evaluated with this procedure. Many of the newer low-stress epoxy formulations gave metal deformation equal to or greater than the standard formulations. One of the materials, however, yielded no observable metal deformation under the test conditions. Metal deformation is a result of shear stress acting at the chip surface, with the direction of the deformation being toward the center of the chip. Microscopic cross-sectional analysis of temperature cycled packages revealed microcracks in the plastic which appeared to have initiated at the chip edge. In most cases, the cracks were about 400/ m long and thus did not reach the package surface. The microcracks appear to promote metal deformation, since they reduce the restrictions on plastic movement at the chip surface. SEM analysis was employed to determine the topography of the deformed aluminum stripes. The effects of chip size, aluminum line width, number of temperature cycles, and post-cure conditions were also determined.